View XCR5032_291507.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APPLICATION NOTE
0
R
XCR5032: 32 Macrocell CPLD
0 14*
DS045 (v1.1) February 10, 2000
Product Specification devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 3V applications, Xilinx also offers the high speed XCR3032 CPLD that offers these features in a full 3V implementation. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 6 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 8 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The XCR5032 CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site). The XCR5032 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others.
Features
* * * * * * * * * * * * * * * * * * Industry's first TotalCMOSTM PLD - both CMOS design and process technologies Fast Zero Power (FZPTM) design technique provides ultra-low power and very high speed High speed pin-to-pin delays of 6 ns Ultra-low static power of less than 75 A 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Two clocks with programmable polarity at every macrocell Support for asynchronous clocking Innovative XPLATM architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed Logic expandable to 37 product terms PCI compliant Advanced 0.5 E2CMOS process Security bit prevents unauthorized access Design entry and verification using industry standard and Xilinx CAE tools Reprogrammable using industry standard device programmers Innovative Control Term structure provides either sum terms or product terms in each logic block for: - Programmable 3-state buffer - Asynchronous macrocell register preset/reset Programmable global 3-state pin facilitates bed of nails' testing without using logic resources Available in both PLCC and VQFP packages Available in both Commercial and Industrial grades
* * *
Description
The XCR5032 CPLD (Complex Programmable Logic Device) is the first in a family of CoolRunnerTM CPLDs from Xilinx. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design technique, the XCR5032 offers true pin-to-pin speeds of 6 ns, while simultaneously delivering power that is less than 75 A at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These DS045 (v1.1) February 10, 2000
www.xilinx.com 1-800-255-7778
1
R
XCR5032: 32 Macrocell CPLD
XPLA Architecture
Figure 1shows a high level block diagram of a 32 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next.
figured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. Each macrocell has five dedicated product terms from the PAL array. The pin-to-pin tPD of the XCR5032 device through the PAL array is 6 ns. This performance is equivalent to the fastest 5V CPLD available today. If a macrocell needs more than five product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 2 ns. So the total pin-to-pin tPD for the XCR5032 using six to 37 product terms is 8 ns (6 ns for the PAL + 2 ns for the PLA).
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. the six control terms can individually be con-
MC0 MC1 I/O MC15 16 16 LOGIC BLOCK 36 ZIA 16 16 36 LOGIC BLOCK
MC0 MC1 I/O MC15
SP00550
Figure 1: Xilinx XPLA CPLD Architecture
DS045 (v1.1) February 10, 2000
www.xilinx.com 1-800-255-7778
2
R
XCR5032: 32 Macrocell CPLD
36 ZIA INPUTS
CONTROL 5
6
PAL ARRAY
PLA ARRAY
(32) SP00435A
Figure 2:
Xilinx XPLA Logic Block Architecture
3
www.xilinx.com 1-800-255-7778
DS045 (v1.1) February 10, 2000
TO 16 MACROCELLS
R
XCR5032: 32 Macrocell CPLD Macrocell Architecture
Figure 2 shows the architecture of the macrocell used in the CoolRunner family. The macrocell consists of a flip-flop that can be configured as either a D- or T-type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunner family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are two clocks (CLK0 and CLK1) available on the XCR5032 device. Clock 0 (CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1) can either be used as a synchronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). The timing for asynchronous clocks is different in that the tCO time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the tSU time is reduced. Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell's flip-flop. The Preset/Reset feature for each macrocell can also be disabled. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied. The other fourcontrol terms (CT2-CT5) can be used to control the Output Enable of the macrocell's output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunner devices are PCI compliant. The macrocell's output buffers can also be always enabled or disabled. All CoolRunner devices also provide a Global 3-State (GTS) pin, which, when enabled and pulled Low, will 3-state all the outputs of the device. This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails" testing. There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated.
TO ZIA
PAL PLA D/T INIT (P or R) Q
GTS GND CT0 CT1 GND CT2 CT3 CT4 CT5 VCC GND SP00440
CLK0 CLK0 CLK1 CLK1
Figure 2: XCR5032 Macrocell Architecture
Terminations
The CoolRunner XCR5032C CPLDs are TotalCMOS devices. As with other CMOS devices, it is important to consider how to properly terminate unused inputs and I/O pins when fabricating a PC board. The XCR5032C devices do not have on-chip termination circuits, so it is recommended that unused inputs and I/O pins be properly terminated. Allowing unused inputs and I/O pins to float can cause the voltage to be in the linear region of the CMOS DS045 (v1.1) February 10, 2000
input structures, which can increase the power consumption of the device. Xilinx recommends the use of 10K pull-up resistors for the termination. Using pull-up resistors allows the flexibility of using these pins should late design changes require additional I/O. These unused pins may also be tied directly to VCC, but this will make it more difficult to reclaim the use of the pin, should this be needed by a subsequent design revision.See the application note Terminating Unused I/O Pins in Xilinx XPLA1 and XPLA2 CoolRunner CPLDs for more information. 4
www.xilinx.com 1-800-255-7778
R
XCR5032: 32 Macrocell CPLD Simple Timing Model
Figure 3 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including tPD, tSU, and tCO. In other architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. For example, in the XCR5032 device, the user knows up front that if a given output uses five product terms or less, the tPD = 6 ns, the tSU = 4.5 ns, and the tCO = 5 ns. If an output is using six to 37 product terms, an additional 2 ns must be added to the tPD and tSU timing parameters to account for the time to propagate through the PLA array.
INPUT PIN
tPD_PAL = COMBINATORIAL PAL ONLY tPD_PLA = COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED tSU_PAL = PAL ONLY tSU_PLA = PAL + PLA
D
Q
REGISTERED tCO
OUTPUT PIN
GLOBAL CLOCK PIN SP00441
Figure 3: CoolRunner Timing Model
5
www.xilinx.com 1-800-255-7778
DS045 (v1.1) February 10, 2000
R
XCR5032: 32 Macrocell CPLD TotalCMOS Design Technique for Fast Zero Power
Xilinx is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 4 and Table 1 showing the ICC vs. Frequency of our XCR5032 TotalCMOS CPLD.
80 TYPICAL
60
ICC (mA)
40
20
0 0 20 40 60 80 100 120 140 160 180
FREQUENCY (MHz) SP00442
ICC vs. 4: V5V, Frequency25C Figure at= CC
Table 1: ICC vs Frequency (VCC = 5V, 25C) Frequency (MHz) Typical ICC (mA) 0 0.05 20 9.62 40 17.5 60 25.6 80 32.5 100 40.8 120 49.0 140 55.9 160 64.2 180 75.2
DS045 (v1.1) February 10, 2000
www.xilinx.com 1-800-255-7778
6
R
XCR5032: 32 Macrocell CPLD
Absolute Maximum Ratings1
Symbol VCC VI VOUT IIN IOUT TJ Tstr
Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. The chip supply voltage must rise monotonically.
Parameter Supply voltage2 Input voltage Output voltage Input current Output current Maximum junction temperature Storage temperature
Min. -0.5 -1.2 -0.5 -30 -100 -40 -65
Max. 7.0 VCC +0.5 VCC +0.5 30 100 150 150
Unit V V V mA mA C C
Operating Range
Product Grade Commercial Industrial Temperature 0 to +70C -40 to +85C Voltage 5V +5% 5V +10%
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0C TAMB +70C; 4.75V VCC 5.25V Symbol VIL VIH VI VOL VOH IIL IIH IIL IOZL IOZH ICCQ1 ICCD1, 2 IOS CIN CCLK CI/O
Notes: 1. See Table 1 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 3. Typical values, not tested.
Parameter Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current low Input leakage current high Clock input leakage current 3-stated output leakage current low 3-stated output leakage current high Standby current Dynamic current Short circuit output current3 Input pin capacitance3 Clock input capacitance3 I/O pin capacitance3
Test Conditions VCC = 4.75V VCC = 5.25V VCC = 4.75V, IIN = -18 mA VCC = 4.75V, IOL = 12 mA VCC = 4.75V, IOH = -12 mA VCC = 5.25V (except CKO), VIN = 0.4V VCC = 5.25V, VIN = 3.0V VCC = 5.25V, VIN = 0.4V VCC = 5.25V, VIN = 0.4V VCC = 5.25V, VIN = 3.0V VCC = 5.25V, TAMB = 0C VCC = 5.25V, TAMB = 0C at 1 MHz VCC = 5.25V, TAMB = 0C at 50 MHz One pin at a time for no longer than 1 second TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz
Min. 2.0
Max. 0.8 -1.2 0.5
2.4 -10 -10 -10 -10 -10
-50
10 10 10 10 10 75 3 30 -200 8 12 10
Unit V V V V V A A A A A A mA mA mA pF pF pF
5
7
www.xilinx.com 1-800-255-7778
DS045 (v1.1) February 10, 2000
R
XCR5032: 32 Macrocell CPLD
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0C TAMB +70C; 4.75V VCC 5.25V Symbol tPD_PAL Parameter 6 7 10 Unit Min. Max. Min. Max. Min. Max. 2 6 2 7.5 2 10 ns 3 2 4 6 3 3 20 20 167 125 105 1.5 4.5 6.5 4 50 11 11 11 14 125 91 80 1.5 6 8.5 5.5 50 12.5 12.5 12.5 15.5 8 5.5 3 2 5.5 8 4 4 20 20 100 64 59 1.5 8.5 11 7.5 50 15 15 15 18 10 7 3 2 8 10.5 5 5 20 20 12.5 9 ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
Propagation delay time, input (or feedback node) to output through PAL tPD_PLA Propagation delay time, input (or feedback node) to output through PAL + PLA tCO Clock to out (global synchronous clock from pin) tSU_PAL Setup time (from input or feedback node) through PAL tSU_PLA Setup time (from input or feedback node) through PAL + PLA tH Hold time tCH Clock High time tCL Clock Low time tR Input rise time Input fall time tF fMAX1 Maximum FF toggle rate2 (1/tCH + tCL) fMAX2 Maximum internal frequency2 (1/tSUPAL + tCF) fMAX3 Maximum external frequency2 (1/tSUPAL + tCO) tBUF Output buffer delay time tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL + PLA Clock to internal feedback node delay time tCF tINIT Delay from valid VCC to valid reset tER Input to output disable2, 3 Input to output valid2 tEA tRP Input to register preset2 tRR Input to register reset2
Notes:
0
0
0
1. Specifications measured with one output switching. See Figure 5 and Table 2 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5 pF.
DS045 (v1.1) February 10, 2000
www.xilinx.com 1-800-255-7778
8
R
XCR5032: 32 Macrocell CPLD
DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40C TAMB +85C; 4.5V VCC 5.5V Symbol VIL VIH VI VOL VOH IIL IIH IIL IOZL IOZH ICCQ1 ICCD1, 2 IOS CIN CCLK CI/O
Notes: 1. See Table 1 on page 6 for typical values. 2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 3. Typical values, not tested.
Parameter Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current low Input leakage current high Clock input leakage current 3-stated output leakage current low 3-stated output leakage current high Standby current Dynamic current Short circuit output current3 Input pin capacitance3 Clock input capacitance3 I/O pin capacitance3
Test Conditions VCC = 4.5V VCC = 5.5V VCC = 4.5V, IIN = -18 mA VCC = 4.5V, IOL = 12 mA VCC = 4.5V, IOH = -12 mA VCC = 5.5V (except CKO), VIN = 0.4V VCC= 5.5V, VIN = 3.0V VCC = 5.5V, VIN = 0.4V VCC= 5.5V, VIN = 0.4V VCC = 5.5V, VIN = 3.0V VCC = 5.5V, TAMB = -40C VCC = 5.5V, TAMB = -40C at 1 MHz VCC = 5.5V, TAMB = -40C at 50 MHz One pin at a time for no longer than 1 second TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz
Min. 2.0
Max. 0.8 -1.2 0.5
2.4 -10 -10 -10 -10 -10
-50
10 10 10 10 10 95 4 35 -230 8 12 10
Unit V V V V V A A A A A A mA mA mA pF pF pF
5
9
www.xilinx.com 1-800-255-7778
DS045 (v1.1) February 10, 2000
R
XCR5032: 32 Macrocell CPLD
AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40C TAMB +85C; 4.5V VCC 5.5V Symbol tPD_PAL tPD_PLA Parameter 7 Min. 2 3 Max. 7.5 9.5 6 Min. 2 3 2 8 10.5 5 5 20 20 100 64 59 1.5 6 8 4.5 50 12 12 12 14 1.5 8.5 11 7.5 50 15 15 15 18 20 20 10 Max. 10 12.5 9 Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
Propagation delay time, input (or feedback node) to output through PAL Propagation delay time, input (or feedback node) to output through PAL + PLA tCO Clock to out (global synchronous clock from pin) 2 tSU_PAL Setup time (from input or feedback node) through PAL 5 tSU_PLA Setup time (from input or feedback node) through PAL + PLA 7 tH Hold time tCH Clock High time 4 Clock Low time 4 tCL tR Input rise time tF Input fall time fMAX1 Maximum FF toggle rate2 (1/tCH + tCL) 125 fMAX2 Maximum internal frequency2 (1/tSUPAL + tCF) 105 fMAX3 Maximum external frequency2 (1/tSUPAL + tCO) 91 Output buffer delay time tBUF tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL+PLA Clock to internal feedback node delay time tCF tINIT Delay from valid VCC to valid reset tER Input to output disable2, 3 tEA Input to output valid2 tRP Input to register preset2 Input to register reset2 tRR
Notes: 1. Specifications measured with one output switching. See Figure 5 and Table 2 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5 pF.
0
0
DS045 (v1.1) February 10, 2000
www.xilinx.com 1-800-255-7778
10
R
XCR5032: 32 Macrocell CPLD
Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
VDD
S1
COMPONENT R1 R2
R1
VALUES 470 250 35 pF
C1
VIN VOUT
MEASUREMENT
R2 C1
S1 Open Closed Closed
S2 Closed Closed Closed
tPZH tPZL tP
S2
NOTE: For tPHZ and tPLZ C = 5pF, and 3-State levels are measured 0.5V from steady state active level.
SP00476
ns 6.60
VCC = 5V, 25C
Voltage Waveform
+3.0V
6.20
90%
10% 0V
TYPICAL 5.80
1.5ns tR tF 1.5ns
SP00368 MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
5.40
Input Pulses
5.00
Table 2: tPD_PAL vs # of Outputs switching (VCC = 5V) # of Outputs
4.60 1 2 4 8 12 16 SP00448A
1 5.1
2 5.2
4 5.5
8 5.9
12 6.1
16 6.3
Typical (ns)
Figure 5: tPD_PAL vs Outputs Switching
11
www.xilinx.com 1-800-255-7778
DS045 (v1.1) February 10, 2000
R
XCR5032: 32 Macrocell CPLD
Pin Function and Layout
Pin Functions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PLCC IN1 IN3 VCC I/O-A0-CK1 I/O-A1 I/O-A2 I/O-A3 I/O-A4 I/O-A5 GND I/O-A6 I/O-A7 I/O-A8 I/O-A9 VCC I/O-A10 I/O-A11 I/O-A12 I/O-A13 I/O-A14 I/O-A15 GND VQFP I/O-A3 I/O-A4 I/O-A5 GND I/O-A6 I/O-A7 I/O-A8 I/O-A9 VCC I/O-A10 I/O-A11 I/O-A12 I/OA13 I/O-A14 I/O-A15 GND VCC I/O-B15 I/O-B14 I/O-B13 I/O-B12 I/O-B11 Pin # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PLCC VCC I/O-B15 I/O-B14 I/O-B13 I/O-B12 I/O-B11 I/O-B10 GND I/O-B9 I/O-B8 I/O-B7 I/O-B6 VCC I/O-B5 I/O-B4 I/O-B3 I/O-B2 I/O-B1 I/O-B0 GND I/O-CK0 IN2-gtsn VQFP I/O-B10 GND I/O-B9 I/O-B8 I/O-B7 I/O-B6 VCC I/O-B5 I/O-B4 I/O-B3 I/O-B2 I/O-B1 I/O-B0 GND IN0/CK0 IN2-gtsn IN1 IN3 VCC
I/O-A0-CK3
I/O-A1 I/O-A2
XCR5032 - 44-pin PLCC
XCR5032 - 44-pin VQFP
6 7
1
40 39 1
44
34 33
PLCC
17 18 28 29 11 12
VQFP
23 22 SP00433A
SP00420A
DS045 (v1.1) February 10, 2000
www.xilinx.com 1-800-255-7778
12
R
XCR5032: 32 Macrocell CPLD
Ordering Information
Example: XCR5032 -6 PC 44 C
Device Type Speed Options Temperature Range Number of Pins Package Type
Speed Options -10: 10 ns pin-to-pin delay -7: 7.5 ns pin-to-pin delay -6: 6 ns pin-to-pin delay
Temperature Range C = Commercial, TA = 0C to +70C I = Industrial, TA = -40C to +85C Packaging Options VQ44: 44-pin VQFP PC44: 44-pin PLCC
Component Availability
Pins Type Code XCR5032 44 Plastic VQFP VQ44 C, I C, I C Plastic PLCC PC44 C, I C, I C
-10 -7 -6
Revision History
Date 9/15/99 2/10/00 Version # 1.0 1.1 Revision Initial Xilinx release. Converted to Xilinx format and updated.
13
www.xilinx.com 1-800-255-7778
DS045 (v1.1) February 10, 2000

▲Up To Search▲

Price & Availability of XCR5032

	To Download XCR5032 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .